Universal Memcomputing in Hardware Realizations of Memristor Cellular Nonlinear Networks



Dr. Vikas Rana

Nr.: RA 3484/1-1

Peter Grünberg Institute at Forschungszentrum Jülich


Prof. Ronald Tetzlaff

Nr.: TE 257/34-1

Chair of Fundamentals of Electrical Engineering, TU Dresden


Performance Analysis of Memristive-CNN based on a VCM Device Model

Yongmin Wang; Alon Ascoli; Ronald Tetzlaff; Vikas Rana; Stephan Menzel

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 27 May 2022 - 01 June 2022, Austin, TX, USA

DOI: 10.1109/ISCAS48785.2022.9937918

Toward Simplified Physics-Based Memristor Modeling of Valence Change Mechanism Devices

Vasileios Ntinas; Alon Ascoli; Ioannis Messaris; Yongmin Wang; Vikas Rana; Stephan Menzel; Ronald Tetzlaff

IEEE Transactions on Circuits and Systems II: Express Briefs (Volume: 69, Issue: 5), 17 March 2022

DOI: 10.1109/TCSII.2022.3160304

A Deep Study of Resistance Switching Phenomena in TaOx ReRAM Cells: System-Theoretic Dynamic Route Map Analysis and Experimental Verification

Alon Ascoli, Stephan Menzel, Vikas Rana, Tim Kempen, Ioannis Messaris, Ahmet Samil Demirkol, Michael Schulten, Anne Siemon, Ronald Tetzlaff

Advanced Electronic Materials, 11 August 2022

DOI: 10.1002/aelm.202200182

System Theory Enables a Deep Exploration of ReRAM Cells' Switching Phenomena

Ronald Tetzlaff; Vikas Rana; Stephan Menzel

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 28 November 2021 - 01 December 2021, Dubai, United Arab Emirates

DOI: 10.1109/ICECS53924.2021.9665611

Project Description

In state-of-the-art von-Neumann computing architectures, the central processing unit (CPU) and the memory are physically separated and communicate only via a finite-bandwidth data bus. In the Internet-of-Things and Big Data processing era, however, the data transfer becomes the limiting factor in computing performance. This limitation, also called the von-Neumann bottleneck, poses a serious constraint for novel popular applications requiring a great deal of data transfer. Thus, the research community is exploring new computing paradigms, in which memory and processing unit are integrated one onto the other.

One promising approach is based on the Cellular Nonlinear Network (CNN) computing paradigm. A single CNN cell consists of a capacitance, a resistance, and a number of voltage-controlled current sources. The cells are organized in a 2D or 3D grid, in which only neighboring cells are physically coupled. The network performs different computation tasks on the basis of the coupling and self-coupling arrangements. Back in 1993, T. Roska proposed to add local storage units to each CNN cell to realize a Universal Machine (UM), the first ever demonstration of a non-von Neumann computer.

CNN cells have been implemented in hardware in combination with photodetectors for the development of very efficient visual microprocessors. The integration of memory units into each cell, however, consumes a large space, and, finally, leads to the poor spatial resolution CNN-based vision sensors suffer from. In order to overcome this issue, very simple non-volatile memory elements with high scalability are required. Memristive devices, especially based on redox mechanisms, show such properties and, thus, they could be the ideal technology candidate to resolve the area-based performance limitation of state-of-the-art CNN-UMs.So far, CNN-UMs have been analyzed only on a theoretical and simulation domain, while a verification in hardware is still missing.

In the proposed Mem2CNN project, the feasibility of Memristor CNN-UM (MCNN-UM) is explored. To this end, the group at TU Dresden teams up with the group at FZ Jülich, combining expertise on memristor and CNN theory (TU Dresden), and on memristor fabrication and physical modeling of memristive devices (FZJ). In the project, the physical compact models of FZJ will be reformulated to enable a more fundamental theoretical framework for memristive circuit modeling and investigation. Moreover, single M-CNN cells will be fabricated and characterized for the first time. For this purpose, a small hardware demonstrator, consisting of a matrix of 6×6 MCNN cells, will be showcased to demonstrate the execution of various tasks, such as the extraction of corners or edges from an input image. Based on the theoretical framework for MCNNs, larger networks will be designed and simulated to demonstrate the potential for computation universality, versatility, and efficiency of the MCNN-UM memcomputing approach.

Further involved scientists


Dr. Alon Ascoli

Chair of Fundamentals of Electrical Engineering, TU Dresden


Dr. Vasileios Ntinas

Chair of Fundamentals of Electrical Engineering, TU Dresden


Yongmin Wang

Peter Grünberg Institute at Forschungszentrum Jülich