The use of non-volatile and multi-bit memristive devices enables new energy-efficient hardware architectures to meet the ever-increasing demands of modern applications. While recent research has mainly demonstrated memristive devices for crossbar arrays and highly efficient in-memory computations, this proposal aims to go a step further to combine the world of analog memristive circuits with reconfigurable digital computer architectures. Therefore, we propose the use of multi-bit SRAM cells to realize new reconfigurable logic architectures (FPGAs) that enable the “quasi-parallel” execution of multiple hardware configurations (multi-context FPGAs). Multi-context FPGAs (MC-FPGAs) enable fast switching between multiple concurrently stored configurations, yet conventional all-digital SRAM-based designs suffer from immense area overhead due to increased memory requirements. Here, the advantages of memristive memories are be fully exploited, thus resulting in a combination of digital logic cells with analog memristive configuration memories. In this application, the multi-level property of RRAM cells is used to realize a reliable 8-state multi-bit RRAM cell and thus multi-context storage for 3 configurations. At the same time, special analog-to-digital converters (ADCs) enable reliable, area- and power-efficient readout. The non-volatility of RRAMs prevents additional power overhead for maintaining inactive configurations. Accordingly, an MC-FPGA with a configuration memory consisting of multi-bit RRAM cells and ADCs will be conceptualized, developed, and evaluated. Only by exploiting the advantages of analog multi-bit RRAMs, it is possible to implement the new and so far unexplored concept of fully RRAM-based multi-context FPGAs and thus meet the ever increasing requirements of modern applications. Thanks to fully CMOS-compatible RRAM technology, not only RRAM cells can be characterized, but also FPGA components combined with memristive configuration memories can be fully evaluated with respect to all critical metrics, including area, power and delay. Based on the non-functional characterization, an iterative design approach built on existing open-source tools will lead to a holistic MC-FPGA platform. Taking the individual evaluation of components one step further, we target an analysis and optimization on system level (complete MC-FPGA platform).