At the end of the 1960s, Leon Chua created the term memristor, an artificial word made up of the words “memory” and “resistor”. According to Chua’s circuit theory, memristor includes all devices whose current/voltage curve runs through the point of origin of the coordinate system and thus, in contrast to other non-volatile memory elements such as ferrite core memories, have a squeezed hysteresis curve. As with all non-volatile memory elements, the state stored in the memristor is not lost even after the operating voltage is switched off.

In addition to the more familiar elements such as resistive ReRAMs (ReRAMs), phase change memories (PCMs) and spin-torque transfer magnetic resistive RAMs (STT-MRAM), this class of memristive components also includes so-called ferroelectric tunnel junction (FTJ) devices. Compared to the other variants mentioned, the latter have the great advantage of generating extremely low readout currents.

It is possible to use this advantage to build embedded AI architectures based on so-called hyperdimensional computing (HDC), which is a kind of alternative to deep neural networks.
In HDC systems, information, e.g. given in the form of individual vectors, is stored distributed in the entries of a very large vector, called a hypervector. Such HDC systems can be used, for example, to analyze EMG signals in order to recognize hand gestures. A large number of e.g. binary entries in the vectors is important.

E.g., such hypervectors can be stored in matrix-shaped crossbar structures. When recognizing a gesture, a large number of elements in a column may have to be read out in parallel and added up. To prevent the currents from becoming too large, it is advisable for the read-out elements to produce only small currents, and this is precisely the case with FTJs.

In order to build crossbar structures in highly integrated mixed-signal chips that can be realized with FTJs in the future, computer architecture studies must be carried out in advance. This allows the crossbar structures to be better evaluated qualitatively and quantitatively. One means of doing this is simulation.

For this reason, the Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) has been working on the project “ReLoFemRis – Reconfigurable Logic and Multi-bit in-memory processing with ferroelectric memristors” as part of the priority program funded by the German Research Foundation (DFG SPP 2262).

In ReLoFemRis, the adaptation of FTJs for computer architectures has generally been researched in recent years and a device and architecture simulator has been developed for that in SystemC.

This simulator was presented at the booth. It has shown how a corresponding architecture can be used for hand gesture recognition.