Memristive Time Difference Encoder (MemTDE)


- Prof. Elisabetta Chicca
- Prof. Regina Dittman

Organic Memcapacitors for Large-Area, Neuromorphic Pattern Recognition: Development of an Electronic Trap System (MemTrap)


- Prof. Frank Ellinger
- Dr.-Ing. Bahman K. Boroujeni
- Prof. Stefan Mannsfeld

Bio inspired Memcomputing via Crossbar Structures (BioMCross)


- Prof. Thomas Mikolajick
- Dr.-Ing. Stefan Slesazeck
- Prof. Ronald Tetzlaff

Hybrid MEMristor-CMOS Micro Electrode Array bio-sensing platform (MEMMEA)


- Dr. Veeresh Deshpande
- Dr.-Ing. Stephan Menzel
- Prof. Roland Thewes
- Dr. Peter Jones

Reconfigurable logic and Multi-bit in-memory processing with ferroelectric memristors (ReLoFeMris)


- Prof. Dietmar Fey
- Dr.-Ing. Stefan Slesazeck

Universal Memcomputing in Hardware Realizations of Memristor Cellular Nonlinear Networks (Mem²CNN)


- Dr.-Ing. Vikas Rana
- Prof. Ronald Tetzlaff

Coordination Funds

Coordination Funds

- Prof. Ronald Tetzlaff

Domino Processing Unit: Towards Novel High Efficient In-Memory-Computing (MemDPU)


- Dr.-Ing. Nan Du
- Dr.-Ing. Stephan Menzel

Memristive In-Memory-Computing: Radiation hard Memory for Computing in Space (MIMEC)


- Prof. Dietmar Fey
- Prof. Amelie Hagelauer
- Dr.-Ing. Marc Reichenbach
- Prof. Christian Wenger

Read more about MIMEC
Robust Compute-in Memory using Memristors (ROBCOMM)


- Prof. Mehdi B. Tahoori
- Dr. Dirk Wouters

Memristive Time Difference Encoder

  • Prof. Elisabetta Chicca (Universität Groningen)
    DFG Project Reference Number (Nr.): CH 1692/5-1
  • Prof. Regina Dittmann (Forschungszentrum Jülich)
    Nr.: DI 919/9-1

In the Internet of Things (IoT) era there is a growing amount of sensory data to be processed. IoT sensors often require the use of wireless communication at the cost of high power consumption. Sensors smart enough to compute data are needed to reduce the communication load and can offer the advantage of local decision making. While there are several advances in the field of sensors and sensor networks, the technology for complex processing at the sensing node is still to be developed, especially for applications requiring compact low-power systems operating with very low latencies.In this project, we will empower a recently proposed computational element, namely the TDE, suitable for low-latency and low-power sensory information processing, with the advantages provided by a hybrid CMOS-memristive implementation. We will engineer volatile redox-based memristive devices with tailored decay times to replace the capacitor used in the CMOS implementation. This will guarantee compactness while enabling the achievement of long time constants (from hundred of milliseconds to seconds) prohibitive for analog CMOS. The combination of short (from microseconds to tens of milliseconds) and long time constants will further extend the field of application of the proposed computational module.This project will take advantage from the synergies of two groups with strongly complementary expertise on memristive device development and analog circuit design.The device engineering and CMOS design efforts planned in this proposal will advance the state-of-the-art in memristive devices and hybrid CMOS-memristive systems. The strategy to engineer the decay times of memristive devices is based on elucidating the details of the redox-processes at the oxide-electrode interface, governing the time stability of the resistive states. The knowledge about the underlying physico-chemical processes causing the time decay will provide novel design rules for both volatile and non-volatile memristive devices in the future.The demonstrator envisioned in this research will enable innovation in smart sensing. We will have the unique opportunity to explore a variety of sensory domains, including vision and audition and possibly touch and olfaction, therefore finding innovative solutions to open sensing problems.

Hybrid MEMristor-CMOS Micro Electrode Array bio-sensing platform

  • Dr. Veeresh Deshpande (Helmholtz-Zentrum Berlin für Materialien und Energie GmbH)
    Nr.: DE 3366/1-1
  • Dr.-Ing. Stephan Menzel (Forschungszentrum Jülich)
    Nr.: ME 4612/2-1
  • Prof. Roland Thewes (FG Sensorik u. Aktuatorik, TU Berlin)
    Nr.: TH 1526/1-1
  • Dr. Peter Jones (NMI an der Universität Tübingen)
    Nr.: ?
Recording of neuronal activities provides a path to understanding brain’s functionality. Chip-based neuronal probes such as CMOS -based micro-electrode arrays (MEA) have made significant progress in recent years providing a platform to record neuronal electrical signals in vitro from multiple sites. This has tremendously progressed neuronal activity recording in real-time. However, it is essential to have low power circuit architecture capable of on-chip neuronal signal processing and electrical stimulation to enable implantable brain stimulation chips. Current CMOS-only neuronal probes have restrictions in power budget to achieve such fully implantable autonomous neuroprosthetics. Therefore, one needs research efforts bringing together energy efficient devices and novel low power circuit design techniques to develop a power efficient system.Memristive devices with their unique characteristics of gradual resistance change, pulse summation, and thresholding behavior can enable compact circuits for neuronal data processing. Therefore, we propose to explore and develop an integrated platform of memristive devices and CMOS MEAs to enable real time power-efficient neuronal sensing probes. This proposal targets on-chip co-integration of memristive devices with CMOS MEA circuits to detect, process neural tissue activity and eventually provide ability for electrical stimulation feedback. In the proposed research, novel memristor-CMOS hybrid circuits will be developed to achieve on-chip signal processing. The development of these new circuit techniques will open doors for broader bio sensing applications.To conduct such an ambitious project, the proposal brings together the best expertise from a broad range of areas: device fabrication and electrical characterization, physical and compact modeling, CMOS circuit design, and in vitro biological characterization. The consortium consists of researchers from HZB, TUB, FZJ, and NMI, leveraging the expertise of four partners who are internationally recognized players in their respective area. In order to demonstrate the neuronal probe platform following objectives are targeted: Objective 1: Development of smart neuron sensors through fabrication of memristive devices on top of CMOS micro-electrode array (MEA) neuron activity sensing chips.Objective 2: Development of a memristive device compact model based on fabricated device characteristics and utilization for circuit design. Objective 3: Optimization of memristive device architecture to achieve power efficient and reliable processing of biological neuronal signals (spike detection in single cells and populations).Objective 4: Characterization of memristive device response to wide range of pulse widths generated on-chip (down to ~1 ns) to advance device physics understanding as well as compact model optimization.The ultimate vision of the proposal is to develop an energy efficient bio-sensing platform based on memristive device-CMOS hybrid circuits.

Domino Processing Unit: Towards Novel High Efficient In-Memory-Computing

  • Dr.-Ing. Nan Du (FSU Jena)
    Nr.: DU 1896/3-1
  • Dr.-Ing. Stephan Menzel (Forschungszentrum Jülich)
    Nr.: ME 4612/1-1
In the era of Big Data and the Internet of Things (IoT), the capability of cost-efficient real-time large-scale data analysis has been requested as the main prerequisites for the next generation of computing architecture. Memristive devices offer enormous potential for non-volatile memories and neuromorphic computing, and a rising interest is also aroused in using memristive technologies for in-memory computing applications. The proposed project MemDPU aims at the development of novel general purpose Domino Processing Unit (DPU) as unconventional in-memory-computing paradigm with high efficiency for data-intensive applications. This work focuses on the comprehensive comparative investigation of a variety of logic primitives based on abrupt and analog memristors and implements the DPU based computing system in both theoretical simulation and physical experiment domains.Within MemDPU project, four logic concepts are determined in terms of the input and output state variables of logic operation, which are the fundamental classifications for DPU computing paradigm: memristance-input-memristance-output (MIMO), voltage-input-voltage-output (VIVO), voltage-input-memristance-output (VIMO) and memristance-input-voltage-output (MIVO). A variety of binary Boolean logic families based on the defined logic concepts will be comprehensively studied by using analog switching memristors in comparison to abrupt switching memristors. Besides binary logic also ternary logic is considered in MemDPU project exploiting the multibit storage capabilities of memristors.Based on a systematic study of various logic families and logic types, the novel DPU computing paradigm will be developed with MIMO as input and output logic gates, VIVO as the operation gate and MIVO/VIMO as the association gate between MIMO and VIVO. For achieving the maximum DPU system performance, an automatic generic synthesis tool is designed, which optimizes the sequential voltage patterns applied to the memristive cells for the application-oriented goal. Furthermore, as a demonstrator, an n-bit calculator, will be realized by adopting DPU computing system both in simulation and hardware implementation schemes in MemDPU project.MemDPU is a joint project that will strongly benefit from the complementary collaboration of an experimentalist (Nan Du) and a theoretician (Stephan Menzel). Nan Du will provide competences in optimization and physical implementation of electroforming-free analog memristors, design and realization of memristive systems. Stephan Menzel will contribute his rich knowledge in theoretical simulation, optimization and modelling of abrupt memristive devices. Together, the applicants form a unique memristor-oriented research team that includes complementary abilities to comprehensively address the all relevant aspects in this project.

Organic Memcapacitors for Large-Area, Neuromorphic Pattern Recognition: Development of an Electronic Trap System

  • Prof. Frank Ellinger (Inst. f. Grundlagen der Elektrotechnik u. Elektronik, TU Dresden)
    Nr.: EL 506/38-1
  • Dr.-Ing. Bahman Kheradmand Boroujeni (Inst. f. Grundlagen der Elektrotechnik u. Elektronik, TU Dresden)
    Nr.: KH 514/1-1
  • Prof. Stefan Mannsfeld (Center for Advancing Electronics, TU Dresden)
    Nr.: MA 3342/8-1
In this proposal, we want to study the organic circuits integration of a recently developed, novel memory structure, dubbed “pinMOS”, that can be thought of as a hybrid of a conventional p-i-n diode OLED structure and a MOS capacitor. In preliminary experiments we already observe a distinct memcapacitive behavior with a double hysteresis loop in charge-voltage graphs and achieve highly reproducible bias history-dependent capacitive states. With this research, we also want to evaluate and further develop this new device with more complex, system-level applications in mind. In order to accomplish this goal, we will develop this technology in a tight feedback loop between the circuit and device fabrication partner (Mannsfeld) and the device modeling/ circuit design partner (Ellinger, Boroujeni). To steer this research towards a feasible system application, we chose an application that makes use of important technological aspects we want to develop and at the same time bears some societal significance. Since food is always a major need for human life, developing environmentally friendly technologies for enhancing agricultural yields while protecting nature will be a key factor for successful development. The proposed system requires a large-area, distributed network of nano-Watt event-detector circuits with built-in tracking of the impedance history. Memcapacitors do not require static power like memristors and therefore are excellent memory elements for this purpose. During the phase I of this Priority program, we will focus on the development of the integration of memcapacitors and organic transistors (and passives) to form working event-detector circuits and circuit blocks for neuromorphic pattern-recognition in a single pixel. The circuit functionalities will be modeled using tools such as Verilog-A, circuit simulators, MATLAB, and SystemC; and theoretical optimization studies/simulations will be carried out.

Reconfigurable logic and Multi-bit in-memory processing with ferroelectric memristors

  • Prof. Dietmar Fey (Department Informatik, Universität Erlangen)
    Nr.: FE 412/10-1
  • Dr.-Ing. Stefan Slesazeck (NaMLab gGmbH, Dresden)
    Nr.: SL 305/2-1
Given the increasing demand for electronic devices in edge-computing applications and IoT, the energy consumption by data transmission from edge to cloud devices as well as the power consumption within the cloud will further increase, unless edge devices would become efficient enough to directly compute e.g. sensor date directly in places. Therefore, in order to realize an overall reduction of power consumption of the IT sector, and thus to facilitate the reduction of the world wide CO2 emission, it becomes increasingly important to develop electronic technologies that enable very efficient computing in mobile and edge devices. Therefore, novel computing paradigms that adopt non-volatile memory devices are of great interest. Especially for embedded devices it makes sense to execute simple logic operations where the data or the operands are located or are generated, namely in the memory or directly at sensor nodes. Near- and in-memory-computing is in principle an answer to the high energy costs of data transfer operations. The aspired project ReProFeMris pursuits the provision and practical implementation of future memristive ferroelectric technology and its application in future energy-efficient embedded in-memory processing architectures. The memristive ferroelectric technology that is to be exploited in the envisaged project is the ferroelectric tunneling junction (FTJ) that is one of the most power efficient technologies compared e.g. to classical ReRAM, STT-MRAM or PCM, that are under investigation at the present. Our project targets to exploit the unique features of ferroelectric memristive technology like MLC capability and reconfigurable logic for in memory arithmetic processing circuits. More specifically, we aim at the utilization of the ferroelectric tunneling junctions for the realization of non-volatile logic gates. Under consideration of the huge promises for extreme low-power operation that these devices possess, however, we target at leveraging the functionality of such concepts by overcoming the given limitations in limited MLC capability and low-current capability of these devices by means of circuit design. At the end of the first project period various basic arithmetic building blocks for extreme area-saving and energy-efficient reconfigurable memristive in-memory computing circuits as well as MLC feature exploiting circuits shall be realized in hardware and the results shall be published as a technical report which is public available via the web pages of NaMLab and FAU.

Memristive In-Memory-Computing: Radiation hard Memory for Computing in Space

  • Prof. Dietmar Fey (Department Informatik, Universität Erlangen)
    Nr.: FE 412/11-1
  • Prof. Amelie Hagelauer (Lehrst. f. Mikro- und Nanosystemtechnik, Technische Universität München)
    Nr.: HA 7772/3-1
  • Dr.-Ing. Marc Reichenbach (Fachbereich Technische Informatik, Brandenburgisch-Technische Universität, Cottbus-Senftenberg)
    Nr.: RE 4182/2-1
  • Prof. Christian Wenger (IHP GmbH, Frankfurt/Oder)
    Nr.: WE 3594/19-1
Microelectronic circuits used in space applications have to be resilient against radiation effects. The concept Internet-of-Space (IoS) will support the internet access in rural regions. In order to realize this concept, it is crucial to place radiation-hard electronic chips into the orbit, where they have to work reliable. Memristive memory devices are suited for such tasks because these electrical switching properties are based on ions instead of electrons. Besides their resilient properties in terms of radiation hardness, RRAMs are also non-volatile memories (NVM). To achieve the highest reliability of the used CMOS electronics in space or other terrestrial radiation contaminated environments, it is recommendable to store the content of the complete computing system in a timely periodic secure back-up store. For this kind of back-up system RRAMs are helpful due to their radiation hardness and the non-volatility of the data stored inside the memory cells in case of a power failure. Non-volatile memory processors, consisting of RRAMs are attractive for IoS applications. In this project, we want to go a step ahead and move some of the processing load to the RRAM memory in the sense of an in-memory computing concept. The in-memory operations will be carried out in the rad-hard sense amplifiers of a RRAM array by signal evaluation and direct integration of memristive RRAM cells in the processing step. To verify the functionality of the radiation-hard system architecture, we are targeting intensive simulation work. In the simulation environment a new model for memristive devices will be used for the investigation of the complete radiation-hard system architecture using in-memory computing for fault detection.The main focus of this proposal is to explore new technological and computational ideas. The radiation hard memory approach with a new non-volatile memory concept, so called RRAM, is the core of this approach. To successfully address this objective, we are also targeting the scope: highly innovative technology leading to improvements in performance and enabling emerging internet-of-space applications.

Bio inspired Memcomputing via Crossbar Structures

  • Prof. Thomas Mikolajick (Inst. f. Halbleiter- u. Mikrosystemtechnik, TU Dresden)
    Nr.: MI 1247/20-1
  • Dr.-Ing. Stefan Slesazeck (NaMLab gGmbH, Dresden)
    Nr.: SL 305/1-1
  • Prof. Ronald Tetzlaff (Inst. f. Grundlagen der Elektrotechnik u. Elektronik, TU Dresden)
    Nr.: TE 257/31-1
The crossbar array, which realizes the matrix-vector multiplication (MVM) operation directly employing the Ohm law, represents the central building block of the non-conventional computing-in-memory (CIM) architectures, such as artificial neural networks (ANNs). The MVM is performed in an analog fashion, and, therefore, it is highly desirable to adopt non-volatile analog switching memristors, leveraging, furthermore, their memcapacitive properties. In this project we aim at the exploitation of the interesting combined memristive and memcapacitive effects in Al2O3 / Nb2O3 based bi-layer device structures, recently developed at NaMLab to be used in conjunction with NFET transistors established at IHM. Based on these devices, we would like to develop a complete design methodology for the implementation of non-conventional versatile computations on a memristive/memcapacitive hardware, which utilizes a hybrid Memristor/Memcapacitor-CMOS architecture, mainly including MVM cores. For this purpose, the proposed work will cover several essential aspects: (i) realization of cells integrating memristive/memcapacitive devices and NFETs, (ii) experimental and theoretical modelling of the single cells, (iii) system-level modelling, analysis, design, and simulation of the MVM core-based ANNs, (iv) derivation of optimization algorithms, that account for the physical limitations of the hardware realization, (v) set-up of efficient instruction sets and peripheral circuitry design, and (vi) optimized mapping of memcomputing tasks onto the ANN structures. In this way, we expect to gain a comprehensive understanding of the feasibility of adopting the aforementioned device concepts in unconventional computing systems, such as multi-layer perceptrons (MLP), convolutional neural networks (CoNN), and recurrent neural networks (ReNN). Finally, we will investigate the possibility of implementing the Quadratic-Integrate-and-Fire (QIF) neuron model in hardware, and to demonstrate the richness of biomimetic dynamical phenomena, which an array of artificial neural structures of this kind may support.

Universal Memcomputing in Hardware Realizations of Memristor Cellular Nonlinear Networks

  • Dr.-Ing. Vikas Rana (Peter Grünberg-Institut am Forschungszentrum Jülich)
    Nr.: RA 3484/1-1
  • Prof. Ronald Tetzlaff (Inst. f. Grundlagen der Elektrotechnik u. Elektronik, TU Dresden)
    Nr.: TE 257/34-1
In state-of-the-art von-Neumann computing architectures, the central processing unit (CPU) and the memory are physically separated and communicate only via a finite-bandwidth data bus. In the Internet-of-Things and Big Data processing era, however, the data transfer becomes the limiting factor in computing performance. This limitation, also called the von-Neumann bottleneck, poses a serious constraint for novel popular applications requiring a great deal of data transfer. Thus, the research community is exploring new computing paradigms, in which memory and processing unit are integrated one onto the other. One promising approach is based on the Cellular Nonlinear Network (CNN) computing paradigm. A single CNN cell consists of a capacitance, a resistance, and a number of voltage-controlled current sources. The cells are organized in a 2D or 3D grid, in which only neighboring cells are physically coupled. The network performs different computation tasks on the basis of the coupling and self-coupling arrangements. Back in 1993, T. Roska proposed to add local storage units to each CNN cell to realize a Universal Machine (UM), the first ever demonstration of a non-von Neumann computer. CNN cells have been implemented in hardware in combination with photodetectors for the development of very efficient visual microprocessors. The integration of memory units into each cell, however, consumes a large space, and, finally, leads to the poor spatial resolution CNN-based vision sensors suffer from. In order to overcome this issue, very simple non-volatile memory elements with high scalability are required. Memristive devices, especially based on redox mechanisms, show such properties and, thus, they could be the ideal technology candidate to resolve the area-based performance limitation of state-of-the-art CNN-UMs.So far, CNN-UMs have been analyzed only on a theoretical and simulation domain, while a verification in hardware is still missing. In the proposed Mem2CNN project, the feasibility of Memristor CNN-UM (MCNN-UM) is explored. To this end, the group at TU Dresden teams up with the group at FZ Jülich, combining expertise on memristor and CNN theory (TU Dresden), and on memristor fabrication and physical modeling of memristive devices (FZJ). In the project, the physical compact models of FZJ will be reformulated to enable a more fundamental theoretical framework for memristive circuit modeling and investigation. Moreover, single M-CNN cells will be fabricated and characterized for the first time. For this purpose, a small hardware demonstrator, consisting of a matrix of 6×6 MCNN cells, will be showcased to demonstrate the execution of various tasks, such as the extraction of corners or edges from an input image. Based on the theoretical framework for MCNNs, larger networks will be designed and simulated to demonstrate the potential for computation universality, versatility, and efficiency of the MCNN-UM memcomputing approach.

Robust Compute-in Memory using Memristors

  • Prof. Mehdi B. Tahoori (Karlsruher Inst. f. Technologie (KIT))
    Nr.: TA 782/36-1
  • Dr. Dirk Wouters (Inst. f. Werkstoffe der Elektrotechnik 2, RWTH Aachen)
    Nr.: WO 2090/1-1
Emerging applications (such as Internet-of-Things and Big Data analytics) are posing serious challenges on current computer architectures and technologies. Therefore, there is an urgent need to explore alternative architectures, not only to further increase the computing efficiency at lower cost, but also to further reduce the overall energy. Further, new device technologies are emerging that, in combination with new architectures, may compete with no-longer-scaling CMOS. Moving computation to memory (data-centric computing) is an emerging computing paradigm shown to have a huge potential in terms of overall computing efficiency. This computing paradigm is also referred to as Computation-in-Memory (CIM). Moving the computation to the memory (rather than doing it in the CPU) will significantly reduce the communication and therefore reduce the power consumption and increase the performance.The most promising solutions for CIM architectures are based on the use of emerging device technologies, such as resistive or magneto-resistive devices, that are able to act as both storage and information processing unit. These, more generally called memristive devices, reduce the overall energy consumption as the devices are non-volatile and the leakages is practically zero, and also they do not require any refresh as it is the case for DRAM, etc. Hence, memristive devices favour increasing system complexity and performance at lower power consumption; thus, providing the scientific community with opportunities for new computer architecture innovations being able to track today’s limitation. However, realizing such a paradigm strongly depends on the development of high quality, reliable and power efficient circuit primitives that enable both storage and computing.This project aims at designing and demonstrating high quality, reliable, robust and energy efficient primitive circuits based on memristive devices to enable computation-in-memory architectures. In particular, we aim at the development of robust CIM circuits based on memristive device by i) carefully modeling and analyzing the effects of memristive device (un)reliability on CIM operation and ii) develop reliability-aware and fault/variation tolerant design of CIM circuits.
  • Prof. Ronald Tetzlaff (Inst. f. Grundlagen der Elektrotechnik u. Elektronik, TU Dresden)
    Nr.: TE 257/35-1
The Priority Programme “Memristive Devices Toward Smart Technical Systems” (MemrisTec, SPP) has been established by the Senate of the Deutsche Forschungsgemeinschaft. The programme will start in 2020 and is planned to run for six years. The project proposal was initiated and coordinated by Prof. Ronald Tetzlaff.We propose a coordination project for the first 3 years of MemrisTec which is dedicated to perform an active stimulation, coordination, and knowledge exchange between the projects but also to build up a software platform for circuit design providing circuit simulation tools based on published memristor models derived within MemrisTec projects. An implemented interactive server will provide software and data in order to ease the communication between project partners. The initiation and coordination of joint scientific publications to be presented in project workshops will be performed within the coordination project. The promotion of young researchers and of gender issues in an international environment represent an important part of planned activities. Finally, an interactive web-page will be implemented and information over social media (Facebook and Twitter) distributed. Special sessions in international conferences (e.g. MEMRISYS, ISCAS) will be organized in cooperation with project partners.